Flip-Flops/Counters MCQs
Practice free Flip-Flops/Counters multiple-choice questions with instant answer feedback and step-by-step solutions. Click an option to check yourself, reveal the full explanation, and work through all 94 questions — no login required.
Question 64easy
Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.
Question 65easy
In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.
Question 66easy
The key to edge-triggered sequential circuits in VHDL is the ________.
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Question 67easy
The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.
Question 68easy
A gated D latch does not have ________.
Question 69easy
Setup time specifies ________.
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Question 70easy
When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:
Question 71easy
Most people would prefer to use ________ over HDL.
Question 72easy
A major drawback to an S -R latch is its ________.