Flip-Flops/Counters MCQs
Practice free Flip-Flops/Counters multiple-choice questions with instant answer feedback and step-by-step solutions. Click an option to check yourself, reveal the full explanation, and work through all 94 questions — no login required.
Question 73easy
In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.
Question 74easy
The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.
Question 75easy
The major advantage of a Schmitt trigger input is that it ________.
Advertisement
Question 76easy
When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.
Question 77easy
Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.
Question 78easy
The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.
Advertisement
Question 79easy
The signal used to identify edge-triggered flip-flops is ________.
Question 80easy
An edge-triggered flip-flop can change states only when ________.
Question 81easy
When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.