Flip-Flops/Counters MCQs

Question 1

The advantage of a J-K flip-flop over an S-R FF is that ________.

Accepted Answer

it has no invalid states

Answer

it has fewer gates

Answer

it has only one output

Answer

it does not require a clock input

Question 2

The ________ is the time interval immediately following the active transition of the clock signal.

Accepted Answer

hold time

Answer

setup time

Answer

over-time

Answer

hang-time

Question 3

A gated S-R flip-flop is in the hold condition whenever ________.

Accepted Answer

the Gate Enable is HIGH and the S and R inputs are both LOW

Answer

the Gate Enable is HIGH

Answer

the Gate Enable is LOW

Answer

the S and R inputs are both LOW

Question 4

The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

Accepted Answer

flip-flop

Answer

logic level

Answer

edge-detector circuit

Answer

toggle detector