Flip-Flops/Counters MCQs

Question 1

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

Accepted Answer

very short.

Answer

very long.

Answer

at a maximum value to enable the input control signals to stabilize.

Answer

of no consequence as long as the levels are within the determinate range of value.

Question 2

A positive edge-triggered D flip-flop will store a 1 when ________.

Accepted Answer

the D input is HIGH and the clock transitions from LOW to HIGH

Answer

the D input is HIGH and the clock transitions from HIGH to LOW

Answer

the D input is HIGH and the clock is LOW

Answer

the D input is HIGH and the clock is HIGH

Question 3

If an input is activated by a signal transition, it is ________

Accepted Answer

edge-triggered

Answer

toggle triggered

Answer

clock triggered

Answer

noise triggered

Question 4

A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?

Accepted Answer

A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.

Answer

The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.

Answer

The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.

Answer

A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.

Question 5

A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms.

Accepted Answer

4.5 K

Answer

45

Answer

455

Answer

455 K

Question 6

Which is not a real advantage of HDL?

Accepted Answer

The use of graphical tools

Answer

Using higher levels of abstraction

Answer

Tailoring components to exactly fit the needs of the project

Answer

Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

Question 7

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.

Accepted Answer

00

Answer

11

Answer

01

Answer

10

Question 8

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

Accepted Answer

cross coupling

Answer

gate impedance

Answer

low input voltages

Answer

asynchronous operation

Question 9

In VHDL, how is each instance of a component addressed?

Accepted Answer

A name followed by a colon and the name of the library primitive

Answer

A name followed by a semicolon and the component type

Answer

A name followed by the library being used

Answer

A name followed by the component library number