Programmable Logic Device MCQs

Question 1

For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.

Accepted Answer

Cp, the same clock input line

Answer

CE, the same clock input line

Answer

PL, the terminal count output

Answer

RC,both clock input lines

Question 2

Which of the following is an invalid output state for an 8421 BCD counter?

Accepted Answer

1110

Answer

0000

Answer

0010

Answer

0001

Question 3

How many different states does a 3-bit asynchronous counter have?

Accepted Answer

8

Answer

2

Answer

4

Answer

16

Question 4

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.

Accepted Answer

60 ns

Answer

12 ms

Answer

24 ns

Answer

48 ns

Question 5

Which of the following procedures could be used to check the parallel loading feature of a counter?

Accepted Answer

Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.

Answer

Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.

Answer

Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.

Answer

Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.

Question 6

One of the major drawbacks to the use of asynchronous counters is:

Accepted Answer

high-frequency applications are limited because of internal propagation delays

Answer

low-frequency applications are limited because of internal propagation delays

Answer

asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications

Answer

asynchronous counters do not have propagation delays and this limits their use in high-frequency applications

Question 7

Three cascaded modulus-5 counters have an overall modulus of ________.

Accepted Answer

125

Answer

5

Answer

25

Answer

500

Question 8

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

Accepted Answer

Fifteen

Answer

None

Answer

One

Answer

Two

Question 9

The final output of a modulus-8 counter occurs one time for every ________.

Accepted Answer

8 clock pulses

Answer

16 clock pulses

Answer

24 clock pulses

Answer

32 clock pulses