Programmable Logic Device MCQs

Question 1

A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

Accepted Answer

500 kHz

Answer

1,500 kHz

Answer

6 MHz

Answer

5 MHz

Question 2

Which segments of a seven-segment display would be required to be active to display the decimal digit 2?

Accepted Answer

a, b, d, e, and g

Answer

a, b, c, d, and g

Answer

a, c, d, f, and g

Answer

a, b, c, d, e, and f

Question 3

How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?

Accepted Answer

64 gates, 6 inputs to each gate

Answer

128 gates, 6 inputs to each gate

Answer

64 gates, 5 inputs to each gate

Answer

128 gates, 5 inputs to each gate

Question 4

A BCD counter is a ________.

Accepted Answer

decade counter

Answer

binary counter

Answer

full-modulus counter

Answer

divide-by-10 counter

Question 5

How many flip-flops are required to construct a decade counter?

Accepted Answer

4

Answer

10

Answer

8

Answer

5

Question 6

The terminal count of a typical modulus-10 binary counter is ________.

Accepted Answer

1001

Answer

0000

Answer

1010

Answer

1111

Question 7

A seven-segment, common-anode LED display is designed for:

Accepted Answer

a HIGH to turn off each segment

Answer

all cathodes to be wired together

Answer

one common LED

Answer

disorientation of segment modules

Question 8

The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:

Accepted Answer

external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs

Answer

modifying BCD counters to change states on every second input clock pulse

Answer

modifying asynchronous counters to change states on every second input clock pulse

Answer

elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts

Question 9

Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.

Accepted Answer

When MR1 and MR2 are both HIGH, all Qs will be reset to zero.

Answer

When MR1 and MR2 are both HIGH, all Qs will be reset to one.

Answer

MR1 and MR2 are provided to synchronously reset all four flip-flops.

Answer

To enable the count mode, MR1 and MR2 must be held LOW.