Programmable Logic Device MCQs

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Practice free Programmable Logic Device multiple-choice questions with instant answer feedback and step-by-step solutions. Click an option to check yourself, reveal the full explanation, and work through all 92 questions — no login required.

Question 28easy
A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?
Question 29easy
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.
Question 30easy
The terminal count of a 3-bit binary counter in the DOWN mode is ________.
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Question 31easy
The hexadecimal equivalent of 15,536 is ________.
Question 32easy
In an HDL ring counter, many invalid states are included in the programming by:
Question 33easy
In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
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Question 34easy
Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Question 35easy
List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.
Question 36easy
Three cascaded decade counters will divide the input frequency by ________.