Flip-Flops/Counters MCQs

Question 1

Which of the following describes the operation of a positive edge-triggered D flip-flop?

Accepted Answer

The output will follow the input on the leading edge of the clock.

Answer

If both inputs are HIGH, the output will toggle

Answer

When both inputs are LOW, an invalid state exists.

Answer

The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

Question 2

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

Accepted Answer

a 10 kHz square wave

Answer

constantly LOW

Answer

constantly HIGH

Answer

a 20 kHz square wave

Question 3

The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

Accepted Answer

opposite, active clock edge

Answer

inverted, positive clock edge

Answer

quiescent, negative clock edge

Answer

reset, synchronous clock edge

Question 4

An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The pulse width (tW) is approximately ________.

Accepted Answer

6.9 ms

Answer

6.9 s

Answer

69 ms

Answer

690 ms

Question 5

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

Accepted Answer

the clock pulse transitions from LOW to HIGH

Answer

the clock pulse is LOW

Answer

the clock pulse is HIGH

Answer

the clock pulse transitions from HIGH to LOW

Question 6

What is the hold condition of a flip-flop?

Accepted Answer

no active S or R input

Answer

both S and R inputs activated

Answer

only S is active

Answer

only R is active

Question 7

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

Accepted Answer

RESET

Answer

SET

Answer

clear

Answer

invalid

Question 8

In VHDL, how many inputs will a primitive JK flip-flop have?

Accepted Answer

5

Answer

2

Answer

3

Answer

4

Question 9

A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

Accepted Answer

CLOCK PGT, D = 1

Answer

CLK = NGT, D = 0

Answer

CLK = PGT, D = 0

Answer

CLOCK NGT, D = 1