Sequential Logic Circuits MCQs
Practice free Sequential Logic Circuits multiple-choice questions with instant answer feedback and step-by-step solutions. Click an option to check yourself, reveal the full explanation, and work through all 22 questions — no login required.
Question 11easy
What is a shift register that will accept a parallel input and can shift data left or right called?
Question 12easy
What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
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Question 14easy
Synchronous construction reduces the delay time of a counter to the delay of __________.
Question 15easy
A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.
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Question 17easy
A sequence of equally spaced timing pulses may be easily generated by a(n) __________.