Sequential Logic Circuits MCQs

22 questionsTechnical-McqsPage 2 of 3

Practice free Sequential Logic Circuits multiple-choice questions with instant answer feedback and step-by-step solutions. Click an option to check yourself, reveal the full explanation, and work through all 22 questions — no login required.

Question 10easy
What is meant by parallel-loading the register?
Question 11easy
What is a shift register that will accept a parallel input and can shift data left or right called?
Question 12easy
What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
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Question 13easy
Mod-6 and mod-12 counters are most commonly used in:
Question 14easy
Synchronous construction reduces the delay time of a counter to the delay of __________.
Question 15easy
A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.
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Question 16easy
In order to use a shift register as a counter, ________.
Question 17easy
A sequence of equally spaced timing pulses may be easily generated by a(n) __________.
Question 18easy
Asynchronous counters are often called ________ counters.