MSI Logic Circuits MCQs

What is the HDL key issue in the design of the MUX and DEMUX?

Why are control inputs included in an HDL magnitude comparator?

What VHDL techniques are used to describe a priority encoder?

What is an important attribute of the conditional signal assignment statement?

There appears to be a problem with a 7-segment display on a DMM sometimes skipping certain numbers. How would you test the display?

What is the purpose of a decoder's inputs?

The circuit in Figure 9-8 is defective; data is not appearing on the output lines. A check with the scope shows data pulses on the serial data line and multiplex control lines, S0–S2; no parity error is indicated. A further check with a logic probe indicates that Vcc and ground appear to be present. What might be wrong with the circuit?

A(n) ________ is a combinational logic circuit that compares two input binary quantities and generates outputs to indicate which one has the greater magnitude.

If by chance more than one of the inputs in an HDL encoder is activated at the same time, the priority encoder ________.