Flip-Flops/Counters MCQs

Question 1

Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.

Accepted Answer

5 kHz

Answer

10.24 kHz

Answer

30.24 kHz

Answer

15 kHz

Question 2

Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

Accepted Answer

The logic level at the D input is transferred to Q on NGT of CLK.

Answer

The Q output is ALWAYS identical to the CLK input if the D input is HIGH.

Answer

The Q output is ALWAYS identical to the D input when CLK = PGT.

Answer

The Q output is ALWAYS identical to the D input.

Question 3

Propagation delay time, tPLH, is measured from the ________.

Accepted Answer

triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

Answer

triggering edge of the clock pulse to the HIGH-to-LOW transition of the output

Answer

preset input to the LOW-to-HIGH transition of the output

Answer

clear input to the HIGH-to-LOW transition of the output

Question 4

How is a J-K flip-flop made to toggle?

Accepted Answer

J = 1, K = 1

Answer

J = 0, K = 0

Answer

J = 1, K = 0

Answer

J = 0, K = 1

Question 5

How many flip-flops are in the 7475 IC?

Accepted Answer

4

Answer

1

Answer

2

Answer

8

Question 6

How many flip-flops are required to produce a divide-by-128 device?

Accepted Answer

7

Answer

1

Answer

4

Answer

6

Question 7

Which is not an Altera primitive port identifier?

Accepted Answer

clr

Answer

clk

Answer

ena

Answer

prn

Question 8

The timing network that sets the output frequency of a 555 astable circuit contains ________.

Accepted Answer

two external resistors and an external capacitor are used

Answer

three external resistors are used

Answer

an external resistor and two external capacitors are used

Answer

no external resistor or capacitor is required

Question 9

The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.

Accepted Answer

ones catching

Answer

parity error checking

Answer

digital discrimination

Answer

digital filtering